1. Field of the Invention
This invention relates to a processor system and, in particular, to a processor having improved facilities for reliably setting a memory address register to a predetermined address. More particularly, this invention relates to processor circuitry for reliably setting a memory address register to a predetermined address upon the receipt of a signal representing a system trouble condition such as, for example, an error representing interrupt request.
2. Description of the Prior Art
The operation of a stored program controlled system requires that its memories reliably respond to the address commands they receive. This applies both to bulk memories comprising separate subsystems (system memory) as well as to hardware memories, often termed microstore memories, internal to the system's processor.
The processor and the system of which the processor is a part normally operates on the assumption (1) that the memory receives valid address information, and (2) that the memory correctly responds to the address information it receives. This assumption is tolerable since normally provided error detection facilities, alarm facilities, and the like generate an error signal if either the system memory or the microstore memory improperly respond to address commands. The generation of an error signal transfer the system from its normal mode of operation to an interrupt mode in which an error handling routine within the microstore is executed to determine the system's response to the trouble condition.
The receipt of an interrupt request representing a system trouble condition makes it is desirable to dispense with the assumption that the memory and the memory addressing facilities are error free and to insert increased error checking into the addressing and control operations for the microstore memory.
It is known how to provide facilities for setting a microstore address register to a specified address in response to the receipt of an interrupt signal. One such arrangement comprises an interrupt request register, a normally set control flip-flop, and an AND gate which is jointly controlled by the output of the register and the flip-flop. The set condition of the flip-flop and the receipt of an interrupt request by the request register transmits a signal through the AND gate to trigger a one-shot multivibrator. This generates a momentary output signal which jams an address register to the microstore address of the first word of an associated interrupt routine. The output of the one-shot multivibrator also resets the control flip-flop to disable the AND gate so that the system cannot respond for the time being to the receipt of any subsequent interrupt request. Instead of a one-shot, a momentary pulse can also be generated logically using the processor clocks to generate a short duration signal.
A typical prior art arrangement is shown on pages 6-22 and 6-23 of INTRODUCTION TO PROGRAMMING, Copyright 1972, Digital Equipment Corporation.
If there are no defects in this prior art circuitry, the contents of the microstore location specified by the address register are read out, subsequent words of the interrupt routine are read out, and the system executes the diagnostic actions built into the routine. The readout of the last word (or a word near the last) of the routine restores the control flip-flop to a set state to partially enable the AND gate so that the system may respond to other interrupt requests.
The foregoing interrupt facilities operate satisfactorily provided they are trouble-free and, in particular, provided that (1) the address register is successfully set to the address of the first word of the interrupt routine and (2) this first word is properly read out of memory. However, it is possible that the address register, or its related circuitry, or the microstore memory could be defective and improperly respond to the interrupt signal. This condition would not be promptly detected by the above described prior art circuit since (1) the output of the one-shot multivibrator could reset the control flip-flop to disable the AND gate and prevent the system from responding to further interrupt requests, (2) the output of the multivibrator might not be successful in setting the address register to the correct address, namely the address of the first word of the interrupt routine or (3) the contents of this first word may not be read out correctly. The system would therefore be locked in an inoperable state in which the address circuitry or microstore memory is inoperable and, at the same time, the reset state of the control flip-flop would prevent the same facilities from responding to any further error associated interrupt requests. It may therefore be seen that the currently available interrupt addressing facilities can contribute to system unreliability.